Following the conclusion of the project, the European Processor Initiative outlines its advancements in sovereign chip technology for supercomputing and artificial intelligence (AI) during a final review in Luxembourg.
The European Processor Initiative, a project of 27 partners, funded by the EuroHPC Joint Undertaking and Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland, concluded successfully four months ago, and has now undergone the final review in Luxembourg.
After four years of the SGA2 project phase, the representatives of the partners presented their work to the reviewers and EuroHPC JU staff. In addition to the standard project review process, this one also had a special item on the schedule.
The review was a special opportunity for the project consortium to showcase the results of their work – especially in the context of two processor families that were being developed – the Arm-based GPP brought up by SiPearl, and the European processor accelerator – EPAC – at the review. This is why the review also organised two types of demonstrations for the reviewers and the EuroHPC JU.
EPAC demo
EPI stream leader Filippo Mantovani led the team in showcasing five different demos to the EuroHPC JU staff and reviewers: a full HPC cluster on the VEC accelerator, EPAC 1.5 test chip as an accelerator using the real taped-out EPAC 1.5 chip as a RISC-V accelerator attached to an Arm host over PCI Express, Kalray KVX use case showing optimised FFT kernels running on their KVX accelerator, Menta demonstrating the optimisation work done on their European EDA tool for large eFPGAs, and finally, ZeroPoint memory compression (DenseMem) on EPAC 1.5. The stream leader presenting said he was thrilled that the team could show it is possible to take RISC-V from IP blocks and into a full HPC software stack. Using those results and presenting them to the community means EPI, after four years of the SGA2 project phase, is making a lasting contribution to the open-hardware ecosystem.
The second processor family, Rhea1, had its world premiere in Luxembourg. The demo showed Rhea1 silicon running a complete HPC software stack shortly after the first silicon was back from the foundry and packaging. This article also now offers more information about the process of bring-up, since Rhea1 returned from the foundry.
SiPearl’s Rhea1 bring-up: Turning European ambition into reality
On 13 May, 2026, a small shipment arrived at SiPearl’s R&D centre in Grenoble (France): it contained the very first Rhea1 CPUs ever manufactured. For the engineers who had spent years defining the architecture, designing the silicon, verifying millions of logic gates and preparing the software stack, this was the moment of truth: the processor existed, and it now had to prove itself.
Rhea1 is one of the most ambitious efforts undertaken in Europe: to design a sovereign high-performance, energy-efficient processor for supercomputing and AI.
Developed by SiPearl as part of the European Processor Initiative consortium, this is Europe’s first-generation CPU built to power exascale European supercomputers.
Integrating 80 Arm Neoverse V1 compute cores, four stacks of High Bandwidth Memory (HBM), four DDR memory controllers, 104 lanes of PCIe Gen5 interface and other advanced HPC technologies, it is the most sophisticated server processor ever designed in Europe.
Designing such a processor is an extraordinary achievement; bringing it to life is a whole different challenge.
The arrival of first silicon marked the start of the bring-up, the moment when years of architecture, hardware design, firmware, and software preparation finally meet reality, as simulations give way to measurements and engineering assumptions become engineering realities.
What followed was an exceptionally fast bring-up. Within a few weeks, SiPearl’s teams reached one milestone after another: first power-on, first clocks, first firmware, first memory access, first PCIe connections, Linux booting across all 80 cores, and finally the execution of the first HPC benchmarks. For a CPU of this complexity, this pace is exceptional, and each milestone strengthened confidence that years of engineering effort were converging toward the first production-ready European HPC processor.
It works.
A key driver of this speed was SiPearl’s pragmatic, iterative strategy: rather than waiting for every subsystem to be fully optimised before enabling software work, the teams made the platform functional as early as possible, enabled software immediately, and improved continuously from real hardware feedback. This let hardware validation, firmware development, Linux integration, and benchmark optimisation progress in parallel.
As of 20 July 2026, the bring-up is still actively underway, with teams now focused on performance characterisation: validating additional features, optimising firmware and software, tuning memory subsystems, and progressively unlocking the processor’s full capabilities.
Industry-standard HPC benchmarks, including STREAM (sustainable memory bandwidth) and HPL (the TOP500 supercomputers benchmark), are currently being conducted and refined, validating not only the raw computing power but the entire hardware and software stack. The first comprehensive performance results are expected later this year, which will mark a major step towards deployment in production.
The bring-up is an important milestone, not the end of the story. Once validation is complete, Rhea1 will be delivered to Bull, which will integrate it into the computing clusters it manufactures to equip JUPITER, the first European exascale supercomputer, owned by EuroHPC JU and hosted and operated by the Jülich Supercomputing Centre in Germany. This deployment marks Rhea1’s first real-world customer integration, with general availability targeted for late 2026.
Beyond the technical achievements, this bring-up highlights a broader issue: Europe’s ability not only to design and develop cutting-edge HPC processors, but to manage the manufacture, integrate, and rapidly commission them. It demonstrates the strength of SiPearl and its EPI partners to deliver strategic technologies for future European supercomputing and AI infrastructure.
Goal: EU sovereignty
The demos and the described bring-up of Rhea1, which is still to be finished, leave us with the thought that the main purpose of EPI is met. The project’s entire goal was to create a consortium that would collaborate on building a low-power microprocessor, a European one. Along the way, industrial partners would build their IP, and scientific partners would strengthen their research, all in the service of making the European digital landscape more sovereign. This task is not finished: even though EPI is concluded, sister projects from EuroHPC JU’s portfolio and other European initiatives, which include many of the partners from the EPI consortium, continue the work on strengthening Europe’s position in the digital space, and some are based on work and research done by EPI.
About EPI
The project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.
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